To improve the reliability of integrated circuits such as memory devices, engineers have developed many stressing and testing procedures to identify defective integrated circuits before they are shipped to customers. Typically, an integrated circuit is formed on a section of a wafer of semiconductor material, such as silicon. Each such section is called a die, and wafer includes multiple dies. For example, a wafer having an 8-inch diameter may include up to 600 individual dies. After the integrated circuits have been formed, the dies are detached, i.e., cut, removed, or scribed, from the wafer along scribe lines. The engineers then subject the individual integrated circuits to the desired testing and stressing procedures. Alternatively, the scribed dies may be packaged before the engineers test the integrated circuits. Integrated circuits that are tested in die form, i.e., before they are packaged, may be packaged after testing and then shipped to customers, or may be shipped to customers in die form, i.e., as known good dies.
The initial stressing of the integrated circuit, often called burn-in, accelerates the physical changes that the circuit would otherwise experience during normal operation, so that a defect that would occur after a number of hours of normal operation often occurs after significantly fewer hours of burn-in. After the completion of the burn-in, engineers test the integrated circuit for defects before it is shipped to a customer. If the engineers find a defect, they may repair the defect if such a repair is possible, or they may discard the defective integrated circuit.
One stressing and testing procedure includes placing a memory circuit into an oven that has a temperature well above room temperature, and then applying to the memory cells within the memory circuit test voltages that are well above the normal operating voltages. To reduce the time of such a procedure, engineers have developed a number of test circuits that are formed as part of the memory circuit and that allow the simultaneous selection of multiple memory cells during the procedure. Examples of such test circuits are described in U.S. patent application Ser. No. 07/954,276, entitled "Stress Test For Memory Arrays In Integrated Circuits," filed Sep. 30, 1992, U.S. Pat. No. 5,341,336, entitled "Method For Stress Testing Decoders And Periphery Circuits," and U.S. Pat. No. 5,339,277, entitled "Address Buffer," which are incorporated by reference.
One problem with known stressing and testing procedures such as the one described above is that they may cause a substantial bottle neck in the overall production of integrated circuits. For example, the number of signal probes that must be coupled to each integrated circuit during stressing and testing often limits the number of integrated circuits that a test station can stress and test at one time. For some large-capacity memory devices, such stress and testing procedures may take approximately 100 hours. Therefore, to decrease the overall stress-test time, one often must use more test stations. However, the size and cost of a test station often makes acquiring additional test stations impractical or impossible. Additionally, if an integrated circuit is stressed and tested after it has been packaged and is found to be defective, the packaging is either removed to allow the repair of the defective circuit, or the defective circuit, package and all, is discarded. Thus, the packaging time and materials are wasted on the defective circuit.